1. Field of the Invention
The present invention pertains to an apparatus and a computer executable program for designing a system Large Scale Integration (system LSI) including a processor configurable in accordance with a target (configurable processor) and to a computer implemented method for verifying integrity between the computer executable programs for the same. In particular, the present invention pertains to a technology for aid to maintain the integrity of a series of the processing programs used for designing the system LSI.
2. Description of the Related Art
Conventionally, in a design of a system LSI, such as a System on Chip (SoC) including a configurable processor in which instructions can be added and/or configurations can be changed according to a target, as for a designer, it is indispensable to describe a source program for an algorithm required of a system for development by using high-level languages, such as C programming language, and to perform a system simulation in a higher level in order to verify functions as the system.
More specifically, as shown in FIG. 1, the designer describes the algorithm in a source program by using the high-level languages in Step S901. In Step S902, the designer selects a configuration of a processor installed in the system LSI, and creates processing programs (design tools), such as a compiler, a simulator and the like. In Step S903, compilation of the source program and a simulation are performed. In Step S904, the designer then verifies whether or not required performance is achieved.
As a result of the verification in Step S904, if the required performance is not achieved, in Step S905, the designer determines whether or not combinations of the processor configurations remain to be verified. If the combinations of the processor configurations remain to be verified, the designer returns to Step S902 and re-designs from selecting the configuration of the processor (in Steps S902 to S904). On the other hand, if all of the combinations of the processor configurations to be verified have been selected, in Step S906, the designer selects a portion to be implemented by hardware and divides the portion to be replaced with the hardware from among functions described in the source program. Then, the designer, in Step S907, retries the compilation of the source program and the system simulation, and, in Step S908, verifies whether or not the required performance is achieved. As a result of the verification in Step S908, if the required performance is not achieved, in Step S909, the designer re-designs including the selection of the algorithm and returns to Step S901.
As a result of the verification in Step S908 or S904, if the required performance is achieved, the work for implementation, such as a tune-up the software, a high-level synthesis, a design by using manpower, and the like, is performed in Step S910.
In the above processing of Step S903 or S907, it is generally performed through the processing procedure including two or more steps, for example, two or more processing programs, such as compiling, assembling, linkage, a simulation or the like. The processing program (design tools) in the each step inputs data (file) generated by the processing program in the previous step. Further, the processing program in the each step inputs required data, inputs the set-up starting option and processes data, according to a target of the each step.
If the data process performed by the processing program is completed normally in each step and a result of the processing satisfies specifications of the system LSI as a target, a processing program (design tool) in the following step performs data processing by using the data (file) generated by the current processing program. If an error is detected in the data processing by the processing program or a result of the processing does not satisfy the specifications of the system LSI as the target, the designer returns to the previous step as needed, corrects the input data etc., and re-performs the processing programs.
As explained above, the data for designing is processed one by one by the two or more processing programs (design tools) in order to design. In particular, in the case of the design of the system LSI including the configurable processor, for example, when the configuration of the processor to be selected, such as cache memory size, an option instruction, etc. is changed, each processing program (design tool) also needs to change according to the changed configuration of the processor.
For this reason, a system LSI design apparatus for generating the design tools which can be processed in a coherent way according to the changed configuration of the processor is disclosed in Japanese patent Laid Open Publication (Kokai) No. 2002-230065.
In the case of designing the system LSI by using such as the design apparatus disclosed in above publication, functions and performance of the source program in which the specification of the system LSI is described are inspected and verified in accordance with the processing procedure of Steps S902 to S905 (or Steps S906 to S908) shown in FIG. 1.
At this stage, since the inspection and verification of the processor, which the composition differs, specified by using configuration information, are performed, the processing programs (design tools) different for every configuration are generated and used respectively as shown in FIG. 2. However, since two or more staffs often share the work such as the inspection and verification, there had been a lack of communication between the staffs accompanying change of the processing programs (design tools). Therefore, as shown in FIG. 4, a human mistake that configuration information [A] of the compiler (C([A]T1-001)) for compiling a source program (foo.c) differs from configuration information [B] of an assembler (A([B]T1-1a)) for assembling a compile result (foo.s) occurs. Consequently, an execution error and/or a malfunction are caused without executing correctly.
Furthermore, in the case that a generation tool for generating processing programs (design tools) is updated from Version T1 to new version T2 in order to improve the performance or to correct a bug as shown in FIG. 3, if mistake of executing with the Version T1 of the compiler (C([A]T1-001)), the assembler (A([A]T1-1a)) and a linker (L([A]T1-10)) differed from the Version T2 of a simulator (S([A]T2-x)) occurs, consequently, an execution error and/or a malfunction are caused as shown in FIG. 5.
As explained above, in the case of designing the system LSI including the configurable processor, since many processing programs (design tools) were generated accompanying the change of the configuration of the processor to be selected and it is necessary to use the generated processing programs properly according to execution environment, it was the problem that enormous amounts of cost and time were required for managing the version, environment, etc. Furthermore, as explained above, since the execution error and malfunction are caused when the processing programs (design tools) of the mistaken version is performed, it was the problem that enormous amounts of cost and time were required for elucidating the cause, re-executing, etc.